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msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 1 post office box 655303 ? dallas, texas 75265 low supply-voltage range, 1.8 v to 3.6 v ultralow-power consumption: active mode: 250 a at 1 mhz, 2.2 v standby mode: 1.1 a off mode (ram retention): 0.1 a five power saving modes wake-up from standby mode in less than 6 s 16-bit risc architecture, 125-ns instruction cycle time 16-bit sigma-delta a/d converter with internal reference and five differential analog inputs 12-bit d/a converter two configurable operational amplifiers 16-bit timer_a with three capture/compare registers brownout detector bootstrap loader serial onboard programming, no external programming voltage needed programmable code protection by security fuse integrated lcd driver with contrast control for up to 56 segments msp430fg42x0 family members include: msp430fg4250: 16kb+256b flash memory 256b ram msp430fg4260: 24kb+256b flash memory 256b ram msp430fg4270: 32kb+256b flash memory 256b ram for complete module descriptions, see msp430x4xx family user?s guide , literature number slau056 for additional device information, see msp430fg42x0 device erratasheet, literature number slaz038 description the texas instruments msp430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. the device features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the digitally controlled oscillator (dco) allows wake-up from low-power modes to active mod e in less than 6 s. the msp430fg42x0 is a microcontroller configuration with a 16-bit timer, a high-performance 16-bit sigma-delta a/d converter, 12-bit d/a converter, two configurable operational amplifiers, 32 i/o pins, and a liquid crystal display driver. typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, hand-held meters, etc. available options packaged devices t a plastic 48-pin ssop (dl) plastic 48-pin qfn (rgz) msp430fg4250idl msp430fg4250irgz ?40 c to 85 c msp430fg4260idl msp430fg4260irgz 40 c to 85 c MSP430FG4270IDL msp430fg4270irgz this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. these devices have limited built-in esd protection. copyright ? 2007, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 2 post office box 655303 ? dallas, texas 75265 pin designation, dl package p5.4/com3 p5.3/com2 p5.2/com1 com0 p2.0/s13/sw0c p2.1/s12/sw1c p2.2/s11 p2.3/s10 p2.4/s9 p2.5/s8 p2.6/s7 p2.7/s6 s5 p5.7/s4 p5.6/s3 p5.5/s2 p5.0/s1 p5.1/s0 lcdcap/r23 lcdref/r13 p1.0/ta0 p1.1/ta0/mclk p1.2/ta1/a4? p1.3/ta2/a4+ tdo/tdi tdi/tclk tms tck rst /nmi dv cc dv ss xin xout av ss av cc v ref p6.0/a0+/oa0o p6.1/a0?/oa0fb p6.2/a1+/oa1o p6.3/a1?/oa1fb p6.4/oa0i1 p6.5/oa0i2 p6.6/oa1i1 p6.7/oa1i2 p1.7/a2+ p1.6/a2?/oa0i0 p1.5/taclk/aclk/a3+ p1.4/a3?/oa1i0/dac0 dl package (top view) msp430fg42x0idl 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 3 post office box 655303 ? dallas, texas 75265 pin designation, rgz package 1 2 3 4 25 14 47 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 34 35 36 46 45 44 43 42 41 40 39 38 dv ss xin xout av cc av ss v ref p6.0/a0+/oa0o p6.1/a0?/oa0fb p6.2/a1+/oa1o p6.3/a1?/oa1fb p6.4/oa0i1 p6.5/oa0i2 p2.2/s11 p2.3/s10 p2.4/s9 p2.5/s8 p2.6/s7 p2.7/s6 s5 p5.7/s4 p5.6/s3 p5.5/s2 p5.0/s1 p5.1/s0 msp430fg42x0irgz p6.6/oa1i1 p6.7/oa1i2 p1.7/a2+ p1.5/taclk/aclk/a3+ p1.6/a2?/oa0i0 p1.4/a3?/oa1i0/dac0 p1.3/ta2/a4+ p1.2/ta1/a4? p1.1/ta0/mclk p1.0/ta0 lcdref/r13 lcdcap/r23 dv cc rst /nmi tck tms tdi/tclk tdo/tdi p5.4/com3 p5.3/com2 p5.2/com1 com0 p2.0/s13/sw0c p2.1/s12/sw1c rgz package (top view)
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 4 post office box 655303 ? dallas, texas 75265 functional block diagram dv cc dv ss av cc av ss rst /nmi p2 flash 32kb 24kb 16kb ram 256b watchdog timer+ wdt+ 15/16-bit port 2 8 i/o interrupt capability por/ brownout basic timer 1 1 interrupt vector lcd_a 56 segments 1,2,3,4 mux 8 mclk xout jtag interface xin smclk aclk mdb mab emulation module p1 port 1 8 i/o interrupt capability 8 sd16_a 16 bit oscillator fll+ 8 mhz cpu incl. 16 registers p5 port 5 8 i/o 8 p6 port 6 8 i/o 8 timer_a3 3 cc reg dac12 12 bit 1 channel voltage out oa0, oa1 2 op amps + gnd switches
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 5 post office box 655303 ? dallas, texas 75265 terminal functions terminal name dl no. rgz no. i/o description tdo/tdi 1 43 i/o test data output. tdo/tdi data output or programming data input terminal tdi/tclk 2 44 i test data input / test clock input. the device protection fuse is connected to tdi/tclk. tms 3 45 i test mode select. tms is used as an input port for device programming and test. tck 4 46 i test clock. tck is the clock input port for device programming and test. rst /nmi 5 47 i general-purpose digital i/o / reset input / nonmaskable interrupt input dv cc 6 48 digital supply voltage, positive terminal dv ss 7 1 digital supply voltage, negative terminal xin 8 2 i input terminal of crystal oscillator xt1 xout 9 3 o output terminal of crystal oscillator xt1 av ss 10 4 analog supply voltage, negative terminal av cc 11 5 analog supply voltage, positive terminal v ref 12 6 i/o analog reference voltage p6.0/a0+/oa0o 13 7 i/o general-purpose digital i/o / analog input a0+ / oa0 output p6.1/a0?/oa0fb 14 8 i/o general-purpose digital i/o / analog input a0? / oa0 feedback input p6.2/a1+/oa1o 15 9 i/o general-purpose digital i/o / analog input a1+ / oa1 output p6.3/a1?/oa1fb 16 10 i/o general-purpose digital i/o / analog input a1? / oa1 feedback input p6.4/oa0i1 17 11 i/o general-purpose digital i/o / oa0 input multiplexer on ?terminal p6.5/oa0i2 18 12 i/o general-purpose digital i/o / oa0 input multiplexer on ?terminal p6.6/oa1i1 19 13 i/o general-purpose digital i/o / oa1 input multiplexer on ?terminal p6.7/oa1i2 20 14 i/o general-purpose digital i/o / oa1 input multiplexer on ?terminal p1.7/a2+ 21 15 i/o general-purpose digital i/o / analog input a2+ p1.6/a2?/oa0i0 22 16 i/o general-purpose digital i/o / analog input a2? / oa0 input multiplexer on +terminal p1.5/taclk/aclk/a3+ 23 17 i/o general-purpose digital i/o / timer_a, clock signal taclk input / aclk output (divided by 1, 2, 4, or 8) / analog input a3+ p1.4/a3?/oa1i0/dac0 24 18 i/o general-purpose digital i/o / analog input a3? / oa1 input multiplexer on +terminal / dac12 output p1.3/ta2/a4+ 25 19 i/o general-purpose digital i/o / timer_a, capture: cci2a, compare: out2 output / analog input a4+ p1.2/ta1/a4? 26 20 i/o general-purpose digital i/o / timer_a, capture: cci1a, compare: out1 output / analog input a4? p1.1/ta0/mclk 27 21 i/o general-purpose digital i/o / timer_a. capture: cci0b / mclk output. note: ta0 is only an input on this pin / bsl receive p1.0/ta0 28 22 i/o general-purpose digital i/o / timer_a. capture: cci0a input, compare: out0 output / bsl transmit lcdref/r13 29 23 external lcd reference voltage input / input port of third most positive analog lcd level (v4 or v3) lcdcap/r23 30 24 capacitor connection for lcd charge pump / input port of second most positive analog lcd level (v2) p5.1/s0 31 25 i/o general-purpose digital i/o / lcd segment output 0 p5.0/s1 32 26 i/o general-purpose digital i/o / lcd segment output 1 p5.5/s2 33 27 i/o general-purpose digital i/o / lcd segment output 2 p5.6/s3 34 28 i/o general-purpose digital i/o / lcd segment output 3 p5.7/s4 35 29 i/o general-purpose digital i/o / lcd segment output 4 s5 36 30 o lcd segment output 5 p2.7/s6 37 31 i/o general-purpose digital i/o / lcd segment output 6 p2.6/s7 38 32 i/o general-purpose digital i/o / lcd segment output 7
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 6 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal name dl no. rgz no. i/o description p2.5/s8 39 33 i/o general-purpose digital i/o / lcd segment output 8 p2.4/s9 40 34 i/o general-purpose digital i/o / lcd segment output 9 p2.3/s10 41 35 i/o general-purpose digital i/o / lcd segment output 10 p2.2/s11 42 36 i/o general-purpose digital i/o / lcd segment output 11 p2.1/s12/sw1c 43 37 i/o general-purpose digital i/o / lcd segment output 12 / low resistance switch to v ss p2.0/s13/sw0c 44 38 i/o general-purpose digital i/o / lcd segment output 13 / low resistance switch to v ss com0 45 39 o common output. com0?com3 are used for lcd backplanes. p5.2/com1 46 40 i/o general-purpose digital i/o / common output. com0?com3 are used for lcd backplanes. p5.3/com2 47 41 i/o general-purpose digital i/o / common output. com0?com3 are used for lcd backplanes. p5.4/com3 48 42 i/o general-purpose digital i/o / common output. com0?com3 are used for lcd backplanes. qfn pad na none na qfn package pad connection to dv ss is recommended.
general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0 sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6 r7 general-purpose register general-purpose register r8 r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15 msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 7 post office box 655303 ? dallas, texas 75265 short-form description cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to-register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 1 shows examples of the three types of instruction formats. table 2 lists the address modes. table 1. instruction word formats dual operands, source-destination e.g., add r4,r5 r4 + r5 ???> r5 single operands, destination only e.g., call r8 pc ??>(tos), r8??> pc relative jump, un/conditional e.g., jne jump-on-equal bit = 0 table 2. address mode descriptions address mode s d syntax example operation register mov rs,rd mov r10,r11 r10 ?> r11 indexed mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5)?> m(6+r6) symbolic (pc relative) mov ede,toni m(ede) ?> m(toni) absolute mov & mem, & tcdat m(mem) ?> m(tcdat) indirect mov @rn,y(rm) mov @r10,tab(r6) m(r10) ?> m(tab+r6) indirect autoincrement mov @rn+,rm mov @r10+,r11 m(r10) ?> r11 r10 + 2?> r10 immediate mov #x,toni mov #45,toni #45 ?> m(toni) note: s = source d = destination
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 8 post office box 655303 ? dallas, texas 75265 operating modes the msp430 has one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: active mode (am) ? all clocks are active low-power mode 0 (lpm0) ? cpu is disabled aclk and smclk remain active, mclk is available to modules fll+ loop control remains active low-power mode 1 (lpm1) ? cpu is disabled aclk and smclk remain active, mclk is available to modules fll+ loop control is disabled low-power mode 2 (lpm2) ? cpu is disabled mclk, fll+ loop control, and dcoclk are disabled dco?s dc-generator remains enabled aclk remains active low-power mode 3 (lpm3) ? cpu is disabled mclk, fll+ loop control, and dcoclk are disabled dco?s dc-generator is disabled aclk remains active low-power mode 4 (lpm4) ? cpu is disabled aclk is disabled mclk, fll+ loop control, and dcoclk are disabled dco?s dc-generator is disabled crystal oscillator is stopped
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 9 post office box 655303 ? dallas, texas 75265 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the address range 0ffffh to 0ffe0h. the vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. table 3. interrupt sources, flags, and vectors of msp430fg42x0 configuration interrupt source interrupt flag system interrupt word address priority power-up external reset watchdog flash memory pc out-of-range (see note 4) wdtifg keyv (see note 1) reset 0fffeh 15, highest nmi oscillator fault flash memory access violation nmiifg (see notes 1 and 3) ofifg (see notes 1 and 3) accvifg (see notes 1 and 3) (non)maskable (non)maskable (non)maskable 0fffch 14 0fffah 13 sd16_a sd16cctlx sd16ovifg, sd16cctlx sd16ifg (see notes 1 and 2) maskable 0fff8h 12 0fff6h 11 watchdog timer wdtifg maskable 0fff4h 10 0fff2h 9 0fff0h 8 0ffeeh 7 timer_a3 taccr0 ccifg0 (see note 2) maskable 0ffech 6 timer_a3 taccr1 ccifg1 and taccr2 ccifg2, taifg (see notes 1 and 2) maskable 0ffeah 5 i/o port p1 (eight flags) p1ifg.0 to p1ifg.7 (see notes 1 and 2) maskable 0ffe8h 4 dac12 dac12_0ifg (see note 2) maskable 0ffe6h 3 0ffe4h 2 i/o port p2 (eight flags) p2ifg.0 to p2ifg.7 (see notes 1 and 2) maskable 0ffe2h 1 basic timer1 btifg maskable 0ffe0h 0, lowest notes: 1. multiple source flags 2. interrupt flags are located in the module. 3. (non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot di sable it. 4. a reset is generated if the cpu tries to fetch instructions from within the module register memory address range (0h?01ffh) o r from within unused address ranges (msp430fg4270, msp430fg4260: from 0300h to 0bffh and from 01100h to 07fffh, msp430fg4250: from 0300h to 0bffh and from 01100h to 0bfffh).
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 10 post office box 655303 ? dallas, texas 75265 special function registers (sfrs) the msp430 sfrs are located in the lowest address space and are organized as byte-mode registers. sfrs should be accessed with byte instructions. interrupt enable registers 1 and 2 7654 0 ofie wdtie 32 1 rw?0 rw?0 rw?0 address 0h accvie nmiie rw?0 wdtie: watchdog-timer interrupt enable. inactive if watchdog mode is selected. active if watchdog timer is configured as a general-purpose timer. ofie: oscillator-fault-interrupt enable nmiie: nonmaskable-interrupt enable accvie: flash access violation interrupt enable 7654 0 32 1 address 01h rw?0 btie btie: basic timer interrupt enable interrupt flag registers 1 and 2 7654 0 ofifg wdtifg 32 1 rw?0 rw?1 rw?(0) address 02h nmiifg wdtifg: set on watchdog timer overflow (in watchdog mode) or security key violation reset on v cc power-on or a reset condition at the rst /nmi pin in reset mode ofifg: flag set on oscillator fault nmiifg: set via rst /nmi pin 7654 0 32 1 address 03h btifg rw?0 btifg: basic timer flag
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 11 post office box 655303 ? dallas, texas 75265 module enable registers 1 and 2 7654 0 32 1 address 04h 7654 0 32 1 address 05h rw?0,1: legend: rw: bit can be read and written bit can be read and written. it is reset or set by puc. bit can be read and written. it is reset or set by por. sfr bit not present in device rw?(0,1): memory organization msp430fg4250 msp430fg4260 msp430fg4270 memory main: interrupt vector main: code memory size flash flash 16kb 0ffffh ? 0ffe0h 0ffffh ? 0c000h 24kb 0ffffh ? 0ffe0h 0ffffh ? 0a000h 32kb 0ffffh ? 0ffe0h 0ffffh ? 08000h information memory size flash 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h boot memory size rom 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h ram size 256 byte 02ffh ? 0200h 256 byte 02ffh ? 0200h 256 byte 02ffh ? 0200h peripherals 16-bit 8-bit 8-bit sfr 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h bootstrap loader (bsl) the msp430 bsl enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the application report features of the msp430 bootstrap loader , literature number slaa089. bsl function dl package pins rgz package pins data transmit 28 - p1.0 22 - p1.0 data receive 27 - p1.1 21 - p1.1
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 12 post office box 655303 ? dallas, texas 75265 flash memory the flash memory can be programmed via the jtag port, the bootstrap loader, or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: flash memory has n segments of main memory and two segments of information memory (a and b) of 128 bytes each. each segment in main memory is 512 bytes in size. segments 0 to n may be erased in one step, or each segment may be individually erased. segments a and b can be erased individually, or as a group with segments 0 to n. segments a and b are also called information memory. new devices may have some bytes programmed in the information memory (needed for test during manufacturing). the user should perform an erase of the information memory prior to the first use. segment 0 w/ interrupt vectors segment 1 segment 2 segment n-1 segment n segment a segment b main memory information memory 32kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 08400h 083ffh 08200h 081ffh 08000h 010ffh 01080h 0107fh 01000h 24kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 0a400h 0a3ffh 0a200h 0a1ffh 0a000h 010ffh 01080h 0107fh 01000h 16kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 0c400h 0c3ffh 0c200h 0c1ffh 0c000h 010ffh 01080h 0107fh 01000h
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 13 post office box 655303 ? dallas, texas 75265 peripherals peripherals are connected to the cpu through data, address, and control buses and can be handled using all instructions. for complete module descriptions, refer to the msp430x4xx family user?s guide , literature number slau056. oscillator and system clock the clock system in the msp430fg42x0 family of devices is supported by the fll+ module, which includes support for a 32768-hz watch crystal oscillator, an internal digitally-controlled oscillator (dco) and a high-frequency crystal oscillator. the fll+ clock module is designed to meet the requirements of both low system cost and low-power consumption. the fll+ features digital frequency locked loop (fll) hardware that, in conjunction with a digital modulator, stabilizes the dco frequency to a programmable multiple of the watch crystal frequency. the internal dco provides a fast turn-on clock source and stabilizes in less than 6 s. the fll+ module provides the following clock signals: auxiliary clock (aclk), sourced from a 32768-hz watch crystal or a high-frequency crystal main clock (mclk), the system clock used by the cpu sub-main clock (smclk), the sub-system clock used by the peripheral modules aclk/n, the buffered output of aclk, aclk/2, aclk/4, or aclk/8 brownout the brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. the cpu begins code execution after the brownout circuit releases the device reset. however, v cc may not have ramped to v cc(min) at that time. the user must ensure the default fll+ settings are not changed until v cc reaches v cc(min) . digital i/o there are four 8-bit i/o ports implemented?ports p1, p2, p5, and p6: all individual i/o bits are independently programmable. any combination of input, output, and interrupt conditions is possible. edge-selectable interrupt input capability for all the eight bits of ports p1 and p2. read/write access to port-control registers is supported by all instructions. basic timer1 basic t imer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. both timers can be read and written by software. basic timer1 can be used to generate periodic interrupts. lcd driver with regulated charge pump the lcd_a driver generates the segment and common signals required to drive an lcd display. the lcd_a controller has dedicated data memory to hold segment drive information. common and segment signals are generated as defined by the mode. static, 2?mux, 3?mux, and 4?mux lcds are supported by this peripheral. the module can provide a lcd voltage independent of the supply voltage via an integrated charge pump. furthermore, it is possible to control the level of the lcd voltage and thus contrast in software. watchdog timer the primary function of the watchdog timer (wdt+) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 14 post office box 655303 ? dallas, texas 75265 timer_a3 timer_a3 is a 16-bit timer/counter with three capture/compare registers. timer_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_a3 signal connections input pin number device in p ut module module module out p ut output pin number dl rgz device input signal module input name module block module output signal dl rgz dl rgz si gna l i npu t n ame bl oc k si gna l dl rgz 23 - p1.5 17 - p1.5 taclk taclk aclk aclk timer na smclk smclk timer na 23 - p1.5 17 - p1.5 taclk inclk 28 - p1.0 22 - p1.0 ta0 cci0a 28 - p1.0 22 - p1.0 27 - p1.1 21 - p1.1 ta0 cci0b ccr0 ta0 dv ss gnd ccr0 ta0 dv cc v cc 26 - p1.2 20 - p1.2 ta1 cci1a 26 - p1.2 20 - p1.2 26 - p1.2 20 - p1.2 ta1 cci1b ccr1 ta1 dv ss gnd ccr1 ta1 dv cc v cc 25 - p1.3 19 - p1.3 ta2 cci2a 25 - p1.3 19 - p1.3 aclk (internal) cci2b ccr2 ta2 dv ss gnd ccr2 ta2 dv cc v cc sd16_a the sd16_a module supports 16-bit analog-to-digital conversions. the module implements a 16-bit sigma-delta core and reference generator. in addition to external analog inputs, an internal v cc sense and temperature sensor are also available. dac12 the dac12 module is a 12-bit, r-ladder, voltage output dac. the dac12 may be used in 8- or 12-bit mode.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 15 post office box 655303 ? dallas, texas 75265 operational amplifier (oa) the msp430fg42x0 has two configurable low-current general-purpose operational amplifiers. each oa input and output terminal is software-selectable and offers a flexible choice of connections for various applications. the oas primarily support front-end analog signal conditioning prior to analog-to-digital conversion. oa signal connections input pin number device in p ut module module module out p ut output pin number dl rgz device input signal module input name module block module output signal dl rgz dl rgz si gna l i npu t n ame bl oc k si gna l dl rgz 22 - p1.6 16 - p1.6 oa0i0 oa0i0 13 - p6.0 7 - p6.0 17 - p6.4 11 - p6.4 oa0i1 oa0i1 oa0 oa0o 18 - p6.5 12 - p6.5 oa0i2 oa0i2 oa0 oa0o 14 - p6.1 8 - p6.1 oa0fb oa0fb 24 - p1.4 18 - p1.4 oa1i0 oa1i0 15 - p6.0 9 - p6.0 19 - p6.6 13 - p6.6 oa1i1 oa1i1 oa1 oa1o 20 - p6.7 14 - p6.7 oa1i2 oa1i2 oa1 oa1o 16 - p6.1 10 - p6.1 oa1fb oa1fb
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 16 post office box 655303 ? dallas, texas 75265 peripheral file map peripherals with word access watchdog watchdog timer control wdtctl 0120h timer_a3 capture/compare register 2 taccr2 0176h _ capture/compare register 1 taccr1 0174h capture/compare register 0 taccr0 0172h timer_a register tar 0170h capture/compare control 2 tacctl2 0166h capture/compare control 1 tacctl1 0164h capture/compare control 0 tacctl0 0162h timer_a control tactl 0160h timer_a interrupt vector taiv 012eh flash flash control 3 fctl3 012ch flash control 2 fctl2 012ah flash control 1 fctl1 0128h dac12 dac12_0 data dac12_0dat 01c8h dac12_0 control dac12_0ctl 01c0h sd16_a (see also peripherals with byte access) general control channel 0 control interrupt vector word register channel 0 conversion memory sd16ctl sd16cctl0 sd16iv sd16mem0 0100h 0102h 0110h 0112h peripherals with byte access oa/gnd switches switch control register swctl 0cfh oa1 operational amplifier 1 control register 1 operational amplifier 1 control register 0 oa1ctl1 oa1ctl0 0c3h 0c2h oa0 operational amplifier 0 control register 1 operational amplifier 0 control register 0 oa0ctl1 oa0ctl0 0c1h 0c0h sd16_a (see also: peripherals with word access) channel 0 input control analog enable sd16inctl0 sd16ae 0b0h 0b7h lcd_a lcd voltage control 1 lcd voltage control 0 lcd voltage port control 1 lcd voltage port control 0 lcd memory 20 : lcd memory 16 lcd memory 15 : lcd memory 1 lcd control and mode lcdavctl1 lcdavctl0 lcdapctl1 lcdapctl0 lcdm20 : lcdm16 lcdm15 : lcdm1 lcdactl 0afh 0aeh 0adh 0ach 0a4h : 0a0h 09fh : 091h 090h
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 17 post office box 655303 ? dallas, texas 75265 peripheral file map (continued) peripherals with byte access (continued) fll+ clock fll+ control 1 fll_ctl1 054h fll+ control 0 fll_ctl0 053h system clock frequency control scfqctl 052h system clock frequency integrator scfi1 051h system clock frequency integrator scfi0 050h basic timer1 bt counter 2 bt counter 1 bt control btcnt2 btcnt1 btctl 047h 046h 040h port p6 port p6 selection p6sel 037h port p6 direction p6dir 036h port p6 output p6out 035h port p6 input p6in 034h port p5 port p5 selection p5sel 033h port p5 direction p5dir 032h port p5 output p5out 031h port p5 input p5in 030h port p2 port p2 selection p2sel 02eh port p2 interrupt enable p2ie 02dh port p2 interrupt-edge select p2ies 02ch port p2 interrupt flag p2ifg 02bh port p2 direction p2dir 02ah port p2 output p2out 029h port p2 input p2in 028h port p1 port p1 selection p1sel 026h port p1 interrupt enable p1ie 025h port p1 interrupt-edge select p1ies 024h port p1 interrupt flag p1ifg 023h port p1 direction p1dir 022h port p1 output p1out 021h port p1 input p1in 020h special functions sfr module enable 2 me2 005h p sfr module enable 1 me1 004h sfr interrupt flag 2 ifg2 003h sfr interrupt flag 1 ifg1 002h sfr interrupt enable 2 ie2 001h sfr interrupt enable 1 ie1 000h
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 18 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? voltage applied at v cc to v ss ?0.3 v to 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to any pin (see note 1) ?0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . diode current at any device terminal . 2 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg : unprogrammed device ?55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programmed device ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltages referenced to v ss. the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the tdi/tclk pin when blowing the jtag fuse. recommended operating conditions min nom max unit supply voltage during program execution (see note 1), v cc (av cc = dv cc = v cc ) 1.8 3.6 v supply voltage during flash memory programming (see note 1), v cc (av cc = dv cc = v cc ) 2.5 3.6 v supply voltage, v ss (av ss = dv ss = v ss ) 0 0 v operating free-air temperature, t a ?40 85 c lf selected, xts_fll=0 watch crystal 32.768 lfxt1 crystal frequency, f (lfxt1) (see note 2) xt1 selected, xts_fll=1 ceramic resonator 450 8000 khz (see note 2) xt1 selected, xts_fll=1 crystal 1000 8000 processor frequency (signal mclk) f v cc = 1.8 v dc 4.15 mhz processor frequency (signal mclk), f (system) v cc = 3.6 v dc 8 mhz notes: 1. it is recommended to power av cc and dv cc from the same source. a maximum difference of 0.3 v between av cc and dv cc can be tolerated during power up and operation. 2. in lf mode, the lfxt1 oscillator requires a watch crystal. in xt1 mode, lfxt1 accepts a ceramic resonator or a crystal. 1.8 3.6 3 ????? ????? ????? ????? ????? ????? ????? ????? ????? 4.15 mhz 8 mhz supply voltage ? v supply voltage range, msp430fg42x0, during flash memory programming supply voltage range, msp430fg42x0, during program execution 2.5 f system (mhz) figure 1. frequency vs supply voltage, typical characteristic
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 19 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into av cc + dv cc excluding external current parameter test conditions min nom max unit i active mode (see note 1), f (mclk) = f (smclk) = 1 mhz, t 40 cto85 c v cc = 2.2 v 250 370 a i (am) f (mclk) = f (smclk) = 1 mhz , f (aclk) = 32,768 hz xts=0, selm=(0,1) t a = ?40 c to 85 c v cc = 3 v 400 520 a i low-power mode (lpm0) t 40 cto85 c v cc = 2.2 v 55 70 a i (lpm0) low power mode (lpm0) (see note 1 and note 4) t a = ?40 c to 85 c v cc = 3 v 95 110 a i low-power mode (lpm2), f (mclk) = f (smclk) = 0 mhz, t 40 cto85 c v cc = 2.2 v 11 14 a i (lpm2) f (mclk) = f (smclk) = 0 mhz , f (aclk) = 32,768 hz, scg0 = 0 (see note 2 and note 4) t a = ?40 c to 85 c v cc = 3 v 17 22 a t a = ?40 c 1.0 2.0 low - power mode (lpm3), t a = 25 c v 22v 1.1 2.0 low - power mode (lpm3) , f (mclk) = f (smclk) = 0 mhz, t a = 60 c v cc = 2.2 v 2.0 3.0 i f (mclk) f (smclk) 0 mhz, f (aclk) = 32,768 hz, scg0 = 1 basic timer1 enabled aclk selected t a = 85 c 3.5 6.0 a i (lpm3) basic timer1 enabled, aclk selected lcd a enabled , lcdcpen = 0 t a = ?40 c 1.8 2.8 a lcd _ a enabled , lcdcpen = 0 (static mode, f lcd = f (aclk) /32), t a = 25 c v 3v 1.6 2.7 (, lcd (aclk) ), (see note 2, note 3, and note 4) t a = 60 c v cc = 3 v 2.5 3.5 t a = 85 c 4.2 7.5 low - power mode (lpm3), t a = ?40 c 2.5 3.5 low - power mode (lpm3) , f (mclk) = f (smclk) = 0 mhz, t a = 25 c v cc = 2.2 v 2.5 3.5 i f (mclk) f (smclk) 0 mhz, f (aclk) = 32,768 hz, scg0 = 1 basic timer1 enabled aclk selected t a = 85 c v cc 2.2 v 3.8 6.0 a i (lpm3) basic timer1 enabled, aclk selected lcd a enabled , lcdcpen = 0 t a = ?40 c 2.9 4.0 a lcd _ a enabled , lcdcpen = 0 (4-mux mode, f lcd = f (aclk) /32), t a = 25 c v cc = 3 v 2.9 4.0 (, lcd (aclk) ), (see note 2, note 3, and note 4) t a = 85 c v cc 3 v 4.4 7.5 t a = ?40 c 0.1 0.5 t a = 25 c v 22v 0.1 0.5 low-power mode (lpm4) t a = 60 c v cc = 2.2 v 0.7 1.1 i l ow-power mo d e (lpm4) , f (mclk) = 0 mhz, f (smclk) = 0 mhz, t a = 85 c 1.7 3.0 a i (lpm4) f (mclk) = 0 mhz , f (smclk) = 0 mhz , f (aclk) = 0 hz, scg0 = 1 ( nt2 dnt4) t a = ?40 c 0.1 0.8 a (aclk) (see note 2 and note 4) t a = 25 c v 3v 0.1 0.8 t a = 60 c v cc = 3 v 0.8 1.2 t a = 85 c 1.9 3.5 notes: 1. timer_a is clocked by f (dcoclk) = f (dco) = 1 mhz. all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. 2. all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. 3. the lpm3 currents are characterized with a micro crystal cc4v?t1a (9 pf) crystal and osccapx = 01h. 4. current for brownout included. current consumption of active mode versus system frequency i (am) = i (am) [1 mhz] f (system) [mhz] current consumption of active mode versus supply voltage i (am) = i (am) [3 v] + 175 a/v (v cc ? 3 v)
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 20 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) schmitt-trigger inputs ? ports p1, p2, p5, and p6; rst /nmi; jtag: tck, tms, tdi/tclk, tdo/tdi parameter test conditions min typ max unit v positive going input threshold voltage v cc = 2.2 v 1.1 1.55 v v it+ positive-going input threshold voltage v cc = 3 v 1.5 1.98 v v negative going input threshold voltage v cc = 2.2 v 0.4 0.9 v v it? negative-going input threshold voltage v cc = 3 v 0.9 1.3 v v input voltage hysteresis (v v ) v cc = 2.2 v 0.3 1.1 v v hys input voltage hysteresis (v it+ ? v it? ) v cc = 3 v 0.5 1 v inputs px.x, tax parameter test conditions v cc min typ max unit t external interrupt timing port p1, p2: p1.x to p2.x, external trigger signal 2.2 v 62 ns t (int) external interrupt timing port p1, p2: p1.x to p2.x, external trigger signal for the interrupt flag, (see note 1) 3 v 50 ns t timer a capture timing ta0 ta1 ta2 2.2 v 62 ns t (cap) timer_a capture timing ta0, ta1, ta2 3 v 50 ns f timer_a clock frequenc y taclk inclk: t =t 2.2 v 8 mhz f (taext) timer _ a clock frequency externally applied to pin taclk, inclk: t (h) = t (l) 3 v 10 mhz f timer a clock frequency smclk or aclk signal selected 2.2 v 8 mhz f (taint) timer_a clock frequency smclk or aclk signal selected 3 v 10 mhz notes: 1. the external signal sets the interrupt flag every time the minimum t (int) parameters are met. it may be set even with trigger signals shorter than t (int) . leakage current ? ports p1, p2, p5, and p6 (see note 1) parameter test conditions min typ max unit i lkg(px.y) leakage current port px v (px.y) (see note 2) v cc = 2.2 v/3 v 50 na notes: 1. the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. 2. the port pin must be selected as input.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 21 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, p5, and p6 parameter test conditions min typ max unit i oh(max) = ?1.5 ma, v cc = 2.2 v, see note 1 v cc ?0.25 v cc v high level output voltage i oh(max) = ?6 ma, v cc = 2.2 v, see note 2 v cc ?0.6 v cc v v oh high-level output voltage i oh(max) = ?1.5 ma, v cc = 3 v, see note 1 v cc ?0.25 v cc v i oh(max) = ?6 ma, v cc = 3 v, see note 2 v cc ?0.6 v cc i ol(max) = 1.5 ma, v cc = 2.2 v, see note 1 v ss v ss +0.25 v low level output voltage i ol(max) = 6 ma, v cc = 2.2 v, see note 2 v ss v ss +0.6 v v ol low-level output voltage i ol(max) = 1.5 ma, v cc = 3 v, see note 1 v ss v ss +0.25 v i ol(max) = 6 ma, v cc = 3 v, see note 2 v ss v ss +0.6 notes: 1. the maximum total current, i oh(max) and i ol(max), for all outputs combined, should not exceed 12 ma to satisfy the maximum specified voltage drop. 2. the maximum total current, i oh(max) and i ol(max), for all outputs combined, should not exceed 48 ma to satisfy the maximum specified voltage drop. output frequency parameter test conditions min typ max unit f (px.y) (x = 1, 2, 5, 6, 0 y 7) c l = 20 pf, i l = 1.5 ma v cc = 2.2 v / 3 v dc f system mhz f (mclk) p1.1/ta0/mclk c l = 20 pf f system mhz p1.1/ta0/mclk , f (mclk) = f (xt1) 40% 60% t (xdc) duty cycle of output frequency p1 . 1/ta0/mclk , c l = 20 pf, v cc = 2.2 v / 3 v f (mclk) = f (dcoclk) 50%? 15 ns 50% 50%+ 15 ns
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 22 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, p5, and p6 (continued) figure 2 v ol ? low-level output voltage ? v 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma t a = ?40 c figure 3 v ol ? low-level output voltage ? v 0 5 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma t a = ?40 c figure 4 v oh ? high-level output voltage ? v ?25 ?20 ?15 ?10 ?5 0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c oh i ? typical high-level output current ? ma t a = ?40 c figure 5 v oh ? high-level output voltage ? v ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c oh i ? typical high-level output current ? ma t a = ?40 c
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 23 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up lpm3 parameter test conditions min typ max unit f = 1 mhz 6 t d ( lpm3 ) delay time f = 2 mhz v cc = 2.2 v/3 v 6 s t d(lpm3) delay time f = 3 mhz v cc 2.2 v/3 v 6 s ram parameter test conditions min typ max unit vramh cpu halted (see note 1) 1.6 v note 1: this parameter defines the minimum supply voltage when the data in program memory ram remain unchanged. no program execution should take place during this supply voltage condition. lcd_a parameter test conditions vcc min typ max unit v cc(lcd) supply voltage charge pump enabled (lcdcpen = 1, vlcdx > 0000) 2.2 3.6 v c lcd capacitor on lcdcap (see note 1) charge pump enabled (lcdcpen = 1, vlcdx > 0000) 4.7 f i cc(lcd) average supply current (see note 2) v lcd(typ) =3v, lcdcpen = 1, vlcdx= 1000, all segments on f lcd = f aclk /32 no lcd connected (see note 3) t a = 25 c 2.2 v 3.8 a f lcd lcd frequency 1.1 khz vlcdx = 0000 vcc vlcdx = 0001 2.60 vlcdx = 0010 2.66 vlcdx = 0011 2.72 vlcdx = 0100 2.78 vlcdx = 0101 2.84 vlcdx = 0110 2.90 v lcd voltage vlcdx = 0111 2.96 v v lcd lcd voltage vlcdx = 1000 3.02 v vlcdx = 1001 3.08 vlcdx = 1010 3.14 vlcdx = 1011 3.20 vlcdx = 1100 3.26 vlcdx = 1101 3.32 vlcdx = 1110 3.38 vlcdx = 1111 3.44 3.60 r lcd lcd driver output impedance v lcd = 3v, lcdcpen = 1, vlcdx = 1000, i load = 10 a 2.2 v 10 k notes: 1. enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device . 2. refer to the supply current specifications i (lpm3) for additional current specifications with the lcd_a module active. 3. connecting an actual display will increase the current consumption depending on the size of the lcd.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 24 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) por/brownout reset (bor) (see note 1) parameter test conditions min typ max unit t d(bor) 2000 s v cc(start) dv cc /dt 3 v/s (see figure 6) 0.7 v (b_it?) v v (b_it?) brownout dv cc /dt 3 v/s (see figure 6 through figure 8) 1.71 v v hys(b_it?) (see note 2) dv cc /dt 3 v/s (see figure 6) 70 130 180 mv t (reset) pulse length needed at rst /nmi pin to accepted reset internally, v cc = 2.2 v/3 v 2 s notes: 1. the current consumption of the brownout module is already included in the i cc current consumption data. the voltage level v (b_it?) + v hys(b_it?) is 1.8v. 2. during power up, the cpu begins code execution following a period of t d(bor) after v cc = v (b_it?) + v hys(b_it?) . the default fll+ settings must not be changed until v cc v cc(min) , where v cc(min) is the minimum supply voltage for the desired operating frequency. see the msp430x4xx family user?s guide (slau056) for more information on the brownout. typical characteristics 0 1 t d(bor) v cc v (b_it?) v hys(b_it?) v cc(start) figure 6. por/brownout reset (bor) vs supply voltage
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 25 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics (continued) v cc(drop) v cc 3 v t pw 0 0.5 1 1.5 2 0.001 1 1000 typical conditions 1 ns 1 ns t pw ? pulse width ? s v cc(drop) ? v t pw ? pulse width ? s v cc = 3 v figure 7. v (cc)min level with a square voltage drop to generate a por/brownout signal v cc 0 0.5 1 1.5 2 v cc(drop) t pw t pw ? pulse width ? s v cc(drop) ? v 3 v 0.001 1 1000 t f t r t pw ? pulse width ? s t f = t r typical conditions v cc = 3 v figure 8. v cc(drop) level with a triangle voltage drop to generate a por/brownout signal
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 26 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) dco parameter test conditions v cc min typ max unit f (dcoclk) n (dco) =01eh, fn_8=fn_4=fn_3=fn_2=0, d = 2, dcoplus= 0, f crystal = 32.768 khz 2.2 v/3 v 1 mhz f fn 8 fn 4 fn 3 fn 2 0 dcoplus 1 2.2 v 0.3 0.65 1.25 mhz f (dco=2) fn_8 = fn_4 = fn_3 = fn_2 = 0, dcoplus = 1 3 v 0.3 0.7 1.3 mhz f fn 8 fn 4 fn 3 fn 2 0 dcoplus 1 2.2 v 2.5 5.6 10.5 mhz f (dco=27) fn_8 = fn_4 = fn_3 = fn_2 = 0, dcoplus = 1 3 v 2.7 6.1 11.3 mhz f fn 8 fn 4 fn 3 0 fn 2 1 dcoplus 1 2.2 v 0.7 1.3 2.3 mhz f (dco=2) fn_8 = fn_4 = fn_3 = 0, fn_2 = 1, dcoplus = 1 3 v 0.8 1.5 2.5 mhz f fn 8 fn 4 fn 3 0 fn 2 1 dcoplus 1 2.2 v 5.7 10.8 18 mhz f (dco=27) fn_8 = fn_4 = fn_3 = 0, fn_2 = 1, dcoplus = 1 3 v 6.5 12.1 20 mhz f fn 8 fn 4 0 fn 3 1 fn 2 x dcoplus 1 2.2 v 1.2 2 3 mhz f (dco=2) fn_8 = fn_4 = 0, fn_3 = 1, fn_2 = x, dcoplus = 1 3 v 1.3 2.2 3.5 mhz f fn 8 fn 4 0 fn 3 1 fn 2 x dcoplus 1 2.2 v 9 15.5 25 mhz f (dco=27) fn_8 = fn_4 = 0, fn_3 = 1, fn_2 = x, dcoplus = 1 3 v 10.3 17.9 28.5 mhz f fn 8 0 fn 4 1 fn 3 fn 2 x dcoplus 1 2.2 v 1.8 2.8 4.2 mhz f (dco=2) fn_8 = 0, fn_4 = 1, fn_3 = fn_2 = x, dcoplus = 1 3 v 2.1 3.4 5.2 mhz f fn 8 0 fn 4 1 fn 3 fn 2 x dcoplus 1 2.2 v 13.5 21.5 33 mhz f (dco=27) fn_8 = 0, fn_4 = 1, fn_3 = fn_2 = x, dcoplus = 1 3 v 16 26.6 41 mhz f fn 8 1 fn 4 fn 3 fn 2 x dcoplus 1 2.2 v 2.8 4.2 6.2 mhz f (dco=2) fn_8 = 1, fn_4 = fn_3 = fn_2 = x, dcoplus = 1 3 v 4.2 6.3 9.2 mhz f fn 8 1 fn 4 fn 3 fn 2 x dcoplus 1 2.2 v 21 32 46 mhz f (dco=27) fn_8= 1, fn_4 = fn_3 = fn_2 = x, dcoplus = 1 3 v 30 46 70 mhz s step size between adjacent dco taps: 1 < tap 20 1.06 1.11 s n step size between adjacent dco taps: s n = f dco(tap n+1) / f dco(tap n) (see figure 10 for taps 21 to 27) tap = 27 1.07 1.17 d temperature drift, n ( d co) = 01eh, fn_8 = fn_4 = fn_3 = fn_2 = 0, 2.2 v ?0.2 ?0.3 ?0.4 % / c d t temperature drift , n (dco) = 01eh , fn _ 8 = fn _ 4 = fn _ 3 = fn _ 2 = 0 , d = 2, dcoplus = 0 (see note 2) 3 v ?0.2 ?0.3 ?0.4 % / c d v drift with v cc variation, n (dco) = 01eh, fn_8 = fn_4 = fn_3 = fn_2 = 0, d = 2, dcoplus = 0 0 5 15 %/v t a ? c v cc ? v f (dco) f (dco20 c) f (dco) f (dco3v) 1.8 3.0 2.4 3.6 1.0 20 60 40 85 1.0 0 ?20 ?40 0 figure 9. dco frequency vs supply voltage v cc and vs ambient temperature
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 27 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? 127 20 1.11 1.17 dco tap s n - stepsize ratio between dco taps min max 1.07 1.06 figure 10. dco tap step size dco frequency adjusted by bits 2 9 to 2 5 in scfi1 {n {dco} } fn_2=0 fn_3=0 fn_4=0 fn_8=0 fn_2=1 fn_3=0 fn_4=0 fn_8=0 fn_2=x fn_3=1 fn_4=0 fn_8=0 fn_2=x fn_3=x fn_4=1 fn_8=0 fn_2=x fn_3=x fn_4=x fn_8=1 legend tolerance at tap 27 tolerance at tap 2 overlapping dco ranges: uninterrupted frequency range f (dco) figure 11. five overlapping dco ranges controlled by fn_x bits
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 28 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) crystal oscillator, lfxt1 oscillator (see notes 1 and 2) parameter test conditions min typ max unit osccapx = 0h, v cc = 2.2 v / 3 v 0 c inte g rated input capacitance osccapx = 1h, v cc = 2.2 v / 3 v 10 pf c xin integrated input capacitance (see note 4) osccapx = 2h, v cc = 2.2 v / 3 v 14 pf osccapx = 3h, v cc = 2.2 v / 3 v 18 osccapx = 0h, v cc = 2.2 v / 3 v 0 c inte g rated output capacitance osccapx = 1h, v cc = 2.2 v / 3 v 10 pf c xout integrated output capacitance (see note 4) osccapx = 2h, v cc = 2.2 v / 3 v 14 pf osccapx = 3h, v cc = 2.2 v / 3 v 18 v il input levels at xin v 2 2 v/3 v (see note 3) v ss 0.2 v cc v v ih input levels at xin v cc = 2.2 v/3 v (see note 3) 0.8 v cc v cc v notes: 1. the parasitic capacitance from the package and board may be estimated to be 2 pf. the effective load capacitor for the crystal is (c xin c xout ) / (c xin + c xout ). this is independent of xts_fll. 2. to improve emi on the low-power lfxt1 oscillator, particularly in the lf mode (32 khz), the following guidelines should be ob served. ? keep as short of a trace as possible between the ?fg42x0 and the crystal. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ? avoid running pcb traces underneath or adjacent to the xin and xout pins. ? use assembly materials and praxis to avoid any parasitic load on the oscillator xin and xout pins. ? if conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. ? do not route the xout line to the jtag header to support the serial programming adapter as shown in other documentation. this signal is no longer required for the serial programming adapter. 3. applies only when using an external logic-level clock source. xts_fll must be set. not applicable when using a crystal or resonator. 4. external capacitance is recommended for precision real-time clock applications, osccapx = 0h.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 29 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) sd16_a, power supply and recommended operating conditions parameter test conditions v cc min typ max unit av cc analog supply voltage av cc = dv cc av ss = dv ss = 0v 2.5 3.6 v sd16lp = 0, sd16bufx = 00, gain: 1,2 650 950 sd16lp = 0 , f sd16 = 1 mhz, sd16bufx = 00, gain: 4,8,16 730 1100 f sd16 1 mhz, sd16osr = 256 sd16bufx = 00, gain: 32 1050 1550 i analog supply current including sd16lp = 1, f 0 5 mhz sd16bufx = 00, gain: 1 3v 620 930 a i sd16 current including internal reference f sd16 = 0.5 mhz, sd16osr = 256 sd16bufx = 00, gain: 32 3 v 700 1060 a sd16lp = 0, sd16bufx = 01, gain: 1 850 sd16lp = 0 , f sd16 = 1 mhz, sd16bufx = 10, gain: 1 1130 f sd16 1 mhz, sd16osr = 256 sd16bufx = 11, gain: 1 1130 f analog front-end input clock sd16lp = 0 (low power mode disabled) 3v 0.03 1 1.1 mhz f sd16 input clock frequency sd16lp = 1 (low power mode enabled) 3 v 0.03 0.5 mhz sd16_a, input range parameter test conditions v cc min typ max unit v differential full scale bipolar mode, sd16uni = 0 ?v ref /2gain +v ref /2gain mv v id,fsr differential full scale input voltage range unipolar mode, sd16uni = 1 0 +v ref /2gain mv sd16gainx = 1 500 differential input sd16gainx = 2 250 v differential input voltage range for specified sd16refon 1 sd16gainx = 4 125 mv v id specified performance sd16refon=1 sd16gainx = 8 62 mv performance (see note 1) sd16gainx = 16 31 (see note 1) sd16gainx = 32 15 f sd16 = 1mhz, sd16gainx = 1 200 k z input impedance (one input pin f sd16 1mhz, sd16bufx = 00 sd16gainx = 32 3v 75 k z i (one input pin to av ss ) f sd16 = 1mhz, sd16bufx = 01 sd16gainx = 1 3 v > 10 m f sd16 = 1mhz, sd16gainx = 1 300 400 k z differential input impedance f sd16 1mhz, sd16bufx = 00 sd16gainx = 32 3v 100 150 k z id input impedance (in+ to in?) f sd16 = 1mhz, sd16bufx > 00 sd16gainx = 1 3 v > 10 m v absolute input sd16bufx = 00 av ss ? 0.1v av cc v v i absolute input voltage range sd16bufx > 00 av ss av cc ?1.2v v v common-mode sd16bufx = 00 av ss ? 0.1v av cc v v ic common mode input voltage range sd16bufx > 00 av ss av cc ?1.2v v notes: 1. the analog input range depends on the reference voltage applied to v ref . if v ref is sourced externally, the full-scale range is defined by v fsr+ = +(v ref /2)/gain and v fsr? = ?(v ref /2)/gain. the analog input range should not exceed 80% of v fsr+ or v fsr? .
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 30 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) sd16_a, performance (f sd16 = 30khz, sd16refon = 1, sd16bufx = 01) parameter test conditions v cc min typ max unit sd16gainx = 1,signal amplitude = 500mv sd16osrx = 256 84 sinad signal-to-noise + distortion ratio sd16gainx = 1,signal amplitude = 500mv sd16osrx = 512 f in = 2.8hz 3 v 84 db distortion ratio sd16gainx = 1,signal amplitude = 500mv sd16osrx = 1024 84 nominal gain sd16gainx = 1, sd16osrx = 1024 3 v 0.97 1.00 1.02 dg/dt gain temperature drift sd16gainx = 1, sd16osrx = 1024 (see note 1) 3 v 15 ppm/ c dg/dv cc gain supply voltage drift sd16gainx = 1, sd16 osrx = 1024, v cc = 2.5 v to 3.6 v (see note 2) 0.35 %/v notes: 1. calculated using the box method: (max(?40...85 c) ? min(?40...85 c))/min(?40...85 c)/(85c ? (?40 c)) 2. calculated using the box method: (max(2.5...3.6v) ? min(2.5...3.6v))/min(2.5...3.6v)/(3.6v ? 2.5v) sd16_a, performance (f sd16 = 1mhz, sd16osrx = 256, sd16refon = 1, sd16bufx = 00) parameter test conditions v cc min typ max unit sd16gainx = 1,signal amplitude = 500mv 83.5 85 sd16gainx = 2,signal amplitude = 250mv 81.5 84 sinad si g nal-to-noise + sd16gainx = 4,signal amplitude = 125mv f in = 50 hz, 3v 76 79.5 db sinad signal to noise + distortion ratio sd16gainx = 8,signal amplitude = 62mv f in = 50 hz , 100 hz 3 v 73 76.5 db sd16gainx = 16,signal amplitude = 31mv 69 73 sd16gainx = 32,signal amplitude = 15mv 62 69 sd16gainx = 1 0.97 1.00 1.02 sd16gainx = 2 1.90 1.96 2.02 g sd16gainx = 4 3v 3.76 3.86 3.96 g nominal gain sd16gainx = 8 3 v 7.36 7.62 7.84 sd16gainx = 16 14.56 15.04 15.52 sd16gainx = 32 27.20 28.35 29.76 e offset error sd16gainx = 1 3v 0.2 %fsr e os offset error sd16gainx = 32 3 v 1.5 %fsr de /dt offset error temperature sd16gainx = 1 3v 4 20 ppm de os /dt temperature coefficient sd16gainx = 32 3 v 20 100 ppm fsr/ c cmrr common-mode sd16gainx = 1, common-mode input signal: v id = 500 mv, f in = 50 hz, 100 hz 3v > 90 db cmrr common mode rejection ratio sd16gainx = 32, common-mode input signal: v id = 16 mv, f in = 50 hz, 100 hz 3 v > 75 db ac psrr ac power supply rejection ratio sd16gainx = 1, v cc = 3 v 100 mv, f vcc = 50 hz 3 v > 80 db
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 31 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) sd16_a, temperature sensor parameter test conditions v cc min typ max unit tc sensor sensor temperature coefficient 1.18 1.32 1.46 mv/k v offset,sensor sensor offset voltage ?100 100 mv sttlt temperature sensor voltage at t a = 85 c 435 475 515 v sensor sensor output voltage (see note 2) temperature sensor voltage at t a = 25 c 3 v 355 395 435 mv v sensor ( see n o t e 2) temperature sensor voltage at t a = 0 c 3 v 320 360 400 mv notes: 1. the following formula can be used to calculate the temperature sensor output voltage: v sensor,typ = tc sensor ( 273 + t [ c] ) + v offset,sensor [mv] 2. results based on characterization and/or production test, not tc sensor or v offset,sensor . sd16_a, built-in voltage reference parameter test conditions v cc min typ max unit v ref internal reference voltage sd16refon = 1, sd16vmidon = 0 3 v 1.14 1.20 1.26 v i ref reference supply current sd16refon = 1, sd16vmidon = 0 3 v 175 260 a tc temperature coefficient sd16refon = 1, sd16vmidon = 0 3 v 18 50 ppm/k c ref v ref load capacitance sd16refon = 1, sd16vmidon = 0 (see note 1) 100 nf i load v ref(i) maximum load current sd16refon = 1, sd16vmidon = 0 3 v 200 na t on turn-on time sd16refon = 0?>1, sd16vmidon = 0, c ref = 100 nf 3 v 5 ms dc psr dc power-supply rejection, v ref / v cc sd16refon = 1, sd16vmidon = 0, v cc = 2.5 v to 3.6 v 100 v/v notes: 1. there is no capacitance required on v ref . however, a capacitance of at least 100nf is recommended to reduce any reference voltage noise. sd16_a, reference output buffer parameter test conditions v cc min typ max unit v ref,buf reference buffer output voltage sd16refon = 1, sd16vmidon = 1 3 v 1.2 v i ref,buf reference supply + reference output buffer quiescent current sd16refon = 1, sd16vmidon = 1 3 v 385 600 a c ref(o) required load capacitance on v ref sd16refon = 1, sd16vmidon = 1 470 nf i load,max maximum load current on v ref sd16refon = 1, sd16vmidon = 1 3 v 1 ma maximum voltage variation vs load current |i load | = 0 to 1 ma 3 v ?15 +15 mv t on turn-on time sd16refon = 0?>1, sd16vmidon = 1, c ref = 470 nf 3 v 100 s sd16_a, external reference input parameter test conditions v cc min typ max unit v ref(i) input voltage range sd16refon = 0 3 v 1.0 1.25 1.5 v i ref(i) input current sd16refon = 0 3 v 50 na
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 32 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit dac, supply specifications parameter test conditions v cc min typ max unit av cc analog supply voltage av cc = dv cc , av ss = dv ss = 0 v 2.20 3.60 v dac12ampx = 2, dac12ir=0, dac12_xdat=0800h 50 110 i supply current dac12ampx = 2, dac12ir=1, dac12_xdat = 0800h, v ref,dac12 = av cc 2 2v/3v 50 110 a i dd supply current (see notes 1 and 2) dac12ampx = 5, dac12ir = 1, dac12_xdat = 0800h, v ref,dac12 = av cc 2.2v/3v 200 440 a dac12ampx=7, dac12ir = 1, dac12_xdat = 0800h, v ref,dac12 = av cc 700 1500 psrr power supply rejection ratio (see notes 3 and 4) dac12_xdat = 800h, v ref,dac12 = 1.2v av cc = 100 mv 2.7v 70 db notes: 1. no load at the output pin assuming that the control bits for the shared pins are set properly. 2. current into reference terminals not included. if dac12ir = 1 current flows through the input divider; see reference input specifications. 3. psrr = 20 log { av cc / v dac12_xout }. 4. v ref is applied externally. the internal reference is not used.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 33 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit dac, linearity specifications (see figure 12) parameter test conditions v cc min typ max unit resolution 12-bit monotonic 12 bits inl integral nonlinearity (see note 1) v ref,dac12 = 1.2 v, dac12ampx = 7, dac12ir = 1 2.7 v 2.0 8.0 lsb dnl differential nonlinearity (see note 1) v ref,dac12 = 1.2 v, dac12ampx = 7, dac12ir = 1 2.7 v 0.4 1.0 lsb e o offset voltage w/o calibration (see notes 1, 2) v ref,dac12 = 1.2 v, dac12ampx = 7, dac12ir = 1 2.7 v 20 mv offset voltage with calibration (see notes 1, 2) v ref,dac12 = 1.2 v, dac12ampx = 7, dac12ir = 1 2.7 v 2.5 mv d e(o) /d t offset error temperature coefficient (see note 1) 2.7 v 30 v/c e g gain error (see note 1) v ref,dac12 = 1.2 v 2.7 v 3.50 % fsr d e(g) /d t gain temperature coefficient (see note 1) 2.7 v 10 ppm of fsr/ c time for offset calibration dac12ampx = 2 2.7 v 100 t offset_cal time for offset calibration (see note 3) dac12ampx = 3, 5 2.7 v 32 ms t offset _ cal (see note 3) dac12ampx = 4, 6, 7 2.7 v 6 ms notes: 1. parameters calculated from the best-fit curve from 0x0a to 0xfff. the best-fit curve method is used to deliver coeffici ents ?a? and ?b? of the first order equation: y = a + b*x. v dac12_xout = e o + (1 + e g ) * (v ref,dac12 /4095) * dac12_xdat, dac12ir = 1. 2. the offset calibration works on the output operational amplifier. offset calibration is triggered setting bit dac12calon. 3. the offset calibration can be done if dac12ampx = {2, 3, 4, 5, 6, 7}. the output operational amplifier is switched off with dac12ampx = {0, 1}. it is recommended that the dac12 module be configured prior to initiating calibration. port activity during calibration may effect accuracy and is not recommended. positive negative v r+ gain error offset error dac code dac v out ideal transfer function r load = av cc c load = 100pf 2 dac output figure 12. linearity test load conditions and gain/offset definition
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 34 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit dac, linearity specifications (continued) dac12_xdat ? digital code ?4 ?3 ?2 ?1 0 1 2 3 4 0 512 1024 1536 2048 2560 3072 3584 v cc = 2.2 v, v ref = 1.2v dac12ampx = 7 dac12ir = 1 typical inl error vs digital input data 4095 inl ? integral nonlinearity error ? lsb dac12_xdat ? digital code ?2.0 ?1.5 ?1.0 ?0.5 0.0 0.5 1.0 1.5 2.0 0 512 1024 1536 2048 2560 3072 3584 v cc = 2.2 v, v ref = 1.2v dac12ampx = 7 dac12ir = 1 typical dnl error vs digital input data 4095 dnl ? differential nonlinearity error ? lsb
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 35 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit dac, output specifications parameter test conditions v cc min typ max unit no load, v ref,dac12 = av cc , dac12_xdat = 0h, dac12ir = 1, dac12ampx = 7 0 0.005 v output voltage range no load, v ref,dac12 = av cc , dac12_xdat = 0fffh, dac12ir = 1, dac12ampx = 7 2 2v/3v av cc ?0.05 av cc v v o range (see note 1, figure 15) r load = 3 k , v ref,dac12 = av cc , dac12_xdat = 0h, dac12ir = 1, dac12ampx = 7 2.2v/3v 0 0.1 v r load = 3 k , v ref,dac12 = av cc , dac12_xdat = 0fffh, dac12ir = 1, dac12ampx = 7 av cc ?0.13 av cc c l(dac12) max dac12 load capacitance 2.2v/3v 100 pf i max dac12 2.2v ?0.5 +0.5 ma i l(dac12) max dac12 load current 3v ?1.0 +1.0 ma r load = 3 k , v o/p(dac12) < 0.3 v, dac12ampx = 2, dac12_xdat = 0h 150 250 r o/p(dac12) output resistance (see figure 15) r load = 3 k , v o/p(dac12) > av cc ? 0.3 v dac12_xdat = 0fffh 2.2v/3v 150 250 (see figure 15) r load = 3 k , 0.3 v v o/p(dac12) av cc ? 0.3 v 1 4 notes: 1. data is valid after the offset calibration of the output amplifier. r o/p(dac12_x) max 0.3 av cc av cc ?0.3v v out min r load av cc c load = 100pf 2 i load dac12 o/p(dac12_x) figure 15. dac12_x output resistance tests
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 36 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit dac, reference input specifications parameter test conditions v cc min typ max unit v reference input dac12ir=0 (see notes 1 and 2) 2 2v/3v av cc /3 av cc +0.2 v v ref reference input voltage range dac12ir=1 (see notes 3 and 4) 2.2v/3v av cc av cc +0.2 v ri reference input dac12ir=0 2 2v/3v 20 m ri (vref) reference input resistance dac12ir=1 2.2v/3v 40 48 56 k notes: 1. for a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (av cc ). 2. the maximum voltage applied at reference input voltage terminal v ref = [av cc ? v e(o) ] / [3*(1 + e g )]. 3. for a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (av cc ). 4. the maximum voltage applied at reference input voltage terminal v ref = [av cc ? v e(o) ] / (1 + e g ). 12-bit dac, dynamic specifications, v ref,dac12 = av cc , dac12ir = 1 (see figure 16 and figure 17) parameter test conditions v cc min typ max unit dac12 dac12_xdat = 800h, dac12ampx=0 {2, 3, 4} 60 120 t on dac12 on time dac12 _ xdat = 800h , error v(o) < 0.5 lsb dac12ampx=0 {5, 6} 2.2v/3v 15 30 s t on on time error v(o) < 0.5 lsb (see note 1,figure 16) dac12ampx=0 7 2.2v/3v 6 12 s settling time dac12 xdat dac12ampx=2 100 200 t s ( fs ) settling time, full scale dac12_xdat = 80h f7fh 80h dac12ampx=3,5 2.2v/3v 40 80 s t s(fs) full scale 80h f7fh 80h dac12ampx=4,6,7 2.2v/3v 15 30 s settling time dac12_xdat = dac12ampx=2 5 t s ( c-c ) settling time, code to code dac12 _ xdat = 3f8h 408h 3f8h dac12ampx=3,5 2.2v/3v 2 s t s(c - c) code to code 3f8h 408h 3f8h bf8h c08h bf8h dac12ampx=4,6,7 2.2v/3v 1 s dac12 xdat dac12ampx=2 0.05 0.12 sr slew rate dac12_xdat = 80h f7fh 80h dac12ampx=3,5 2.2v/3v 0.35 0.7 v/ s sr slew rate 80h f7fh 80h dac12ampx=4,6,7 2.2v/3v 1.5 2.7 v/ s dac12 xdat dac12ampx=2 10 glitch energy, full scale dac12_xdat = 80h f7fh 80h dac12ampx=3,5 2.2v/3v 10 nv-s glitch energy, full scale 80h f7fh 80h dac12ampx=4,6,7 2.2v/3v 15 nv s notes: 1. r load and c load connected to av ss (not av cc /2) in figure 16. 2. slew rate applies to output voltage steps 200mv. r load av cc c load = 100pf 2 dac output r o/p(dac12.x) i load conversion 1 conversion 2 v out conversion 3 glitch energy +/? 1/2 lsb +/? 1/2 lsb t settlelh t settlehl = 3 k figure 16. settling time and glitch energy testing
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 37 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) conversion 1 conversion 2 v out conversion 3 10% t srlh t srhl 90% 10% 90% figure 17. slew rate testing 12-bit dac, dynamic specifications (continued) (t a = 25 c unless otherwise noted) parameter test conditions v cc min typ max unit 3 db b d idth dac12ampx = {2, 3, 4}, dac12srefx = 2, dac12ir = 1, dac12_xdat = 800h 40 bw ?3db 3-db bandwidth, v dc =1.5 v, v ac =0.1 v pp (see figure 18) dac12ampx = {5, 6}, dac12srefx = 2, dac12ir = 1, dac12_xdat = 800h 2.2v/3v 180 khz (see figure 18) dac12ampx = 7, dac12srefx = 2, dac12ir = 1, dac12_xdat = 800h 550 notes: 1. r load = 3 k , c load = 100 pf ve ref+ ac dc r load av cc c load = 100pf 2 i load dac12_x dacx = 3 k figure 18. test conditions for 3-db bandwidth specification
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 38 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) operational amplifier oa, supply specifications parameter test conditions v cc min typ max unit v cc supply voltage ? 2.2 3.6 v fast mode 180 290 sl t fast mode 180 290 i su pp l y current medium mode 2 2 v/3 v 110 190 a i cc supply current (see note 1) medium mode 2.2 v/3 v 110 190 a i cc ( see n o t e 1) slow mode 2.2 v/3 v 50 80 a psrr power supply rejection ratio non-inverting 2.2 v/3 v 70 db notes: 1. p6sel.x = 1 or sd16ae.x = 1 for each corresponding pin when used in oa input or oa output mode. operational amplifier oa, input/output specifications parameter test conditions v cc min typ max unit v i/p input voltage, i/p ? ?0.1 v cc ?1.2 v i input leaka g e current, i/p t a = ?40 c to 55 c ?5 0.5 5 na i ikg input leakage current , i/p (see notes 1 and 2) t a = 55 c to 85 c ? ?20 5 20 na fast mode 50 medium mode f v ( i/p ) = 1 khz 80 v voltage noise density i/p slow mode f v(i/p) 1 khz 140 nv/ hz v n voltage noise density, i/p fast mode ? 30 nv/ hz medium mode f v ( i/p ) = 10 khz 50 slow mode f v(i/p) 10 khz 65 v offset voltage i/p 2 2 v/3 v 10 mv v io offset voltage, i/p 2.2 v/3 v 10 mv offset temperature drift, i/p see note 3 2.2 v/3 v 10 v/ c offset voltage drift with supply, i/p 0.3v v in v cc ?0.3 v v cc 10%, t a = 25 c 2.2 v/3 v 1.5 mv/v v high level output voltage o/p fast mode, i source ?500 a 2.2 v v cc ?0.2 v cc v v oh high-level output voltage, o/p slow mode,i source ?150 a 3 v v cc ?0.1 v cc v v low level output voltage o/p fast mode, i source +500 a 2.2 v v ss 0.2 v v ol low-level output voltage, o/p slow mode,i source +150 a 3 v v ss 0.1 v cmrr common-mode rejection ratio non-inverting 2.2 v/3 v 70 db notes: 1. esd damage can degrade input current leakage. 2. the input bias current is overridden by the input leakage current. 3. characterized and calculated using the box method, not production tested.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 39 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) operational amplifier oa, dynamic specifications parameter test conditions v cc min typ max unit fast mode 1.2 sr slew rate medium mode ? 0.8 v/ s sr slew rate slow mode 0.3 v/ s open-loop voltage gain ? 100 db m phase margin c l = 50 pf ? 60 deg gain margin c l = 50 pf ? 20 db noninverting fast mode r 47k c 50pf 22 gain - bandwidth product noninverting, fast mode, r l = 47k , c l = 50pf 2.2 gbw gain - bandwidth product (see figure 19 noninverting medium mode r 300k c 50pf 2 2 v/3 v 14 mhz gbw (see figure 19 noninverting, medium mode, r l =300k , c l = 50pf 2.2 v/3 v 1.4 mhz gbw (see figure 19 a n d fi gu r e 2 0) noninverting slow mode r 300k c 50pf 2.2 v/3 v 05 mhz and figure 20) noninverting, slow mode, r l =300k , c l = 50pf 0.5 t en(on) enable time on t on , noninverting, gain = 1 2.2 v/3 v 10 20 s t en(off) enable time off 2.2 v/3 v 1 s figure 19 input frequency ? khz ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 typical open-loop gain vs frequency slow mode fast mode gain ? db medium mode 0.001 0.01 0.1 1 10 100 1000 10000 figure 20 input frequency ? khz ?250 ?200 ?150 ?100 ?50 0 typical phase vs frequency phase ? degrees slow mode fast mode medium mode 0.001 0.01 0.1 1 10 100 1000 10000 switches to ground parameter test conditions v cc min typ max unit v cc supply voltage 2.5 3.6 v i input leaka g e current t a = ?40 c to + 55 c 1 10 na i lkg input leakage current (see note 1) t a = 55 c to 85 c 50 na i in input current input switched to ground. 0 100 a r on on resistance i in =100 a, t a =?40 c to 85 c 10 notes: 1. esd damage can degrade input current leakage.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 40 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) flash memory parameter test conditions v cc min typ max unit v cc(pgm/ erase) program and erase supply voltage 2.5 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from dv cc during program 2.5v/3.6v 3 5 ma i erase supply current from dv cc during erase 2.5v/3.6v 3 7 ma t cpt cumulative program time see note 1 2.5v/3.6v 10 ms t cmerase cumulative mass erase time see note 2 2.5v/3.6v 200 ms program/erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time 35 t block, 0 block program time for 1 st byte or word 30 t block, 1-63 block program time for each additional byte or word see note 3 21 t t block, end block program end-sequence wait time see note 3 6 t ftg t mass erase mass erase time 5297 t seg erase segment erase time 4819 notes: 1. the cumulative program time must not be exceeded when writing to a 64?byte flash block. this parameter applies to all programming methods: individual word/byte write and block write modes. 2. the mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f ftg ,max = 5297x1/476khz). to achieve the required cumulative mass erase time the flash controller?s mass erase operation can be repeated until this time is met. (a worst case minimum of 19 cycles are required). 3. these values are hardwired into the flash controller?s state machine (t ftg = 1/f ftg ). jtag interface parameter test conditions v cc min typ max unit f tck input frequency see note 1 2.2 v 0 5 mhz f tck tck input frequency see note 1 3 v 0 10 mhz r internal internal pull-up resistance on tms, tck, tdi/tclk see note 2 2.2 v/ 3 v 25 60 90 k notes: 1. f tck may be restricted to meet the timing requirements of the module selected. 2. tms, tdi/tclk, and tck pull-up resistors are implemented in all versions. jtag fuse (see note 1) parameter test conditions v cc min typ max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on tdi/tclk for fuse-blow: f versions 6 7 v i fb supply current into tdi/tclk during fuse blow 100 ma t fb time to blow fuse 1 ms notes: 1. once the fuse is blown, no further access to the msp430 jt ag/t est and emulation features is possible. the jtag block is switched to bypass mode.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 41 post office box 655303 ? dallas, texas 75265 input/output schematics port p1 pin schematic: p1.0, p1.1, input/output with schmitt trigger bus keeper en direction 0: input 1: output p1sel.x 1 0 p1dir.x p1in.x dv ss dv ss pad logic dv ss p1irq.x d en module x in 1 0 module x out p1out.x note: x = 0,1 p1.0/ta0 p1.1/ta0/mclk interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x port p1 (p1.0, p1.1) pin functions pin name (p1 x) x function control bits / signals pin name (p1.x) x function p1dir.x p1sel.x p1.0/ta0 0 p1.0? input/output 0/1 0 timer_a3.cci0a 0 1 timer_a3.ta0 1 1 p1.1/ta0/mclk 1 p1.1? input/output 0/1 0 timer_a3.cci0b 0 1 mclk 1 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 42 post office box 655303 ? dallas, texas 75265 port p1 pin schematic: p1.2, input/output with schmitt trigger and analog functions bus keeper en direction 0: input 1: output p1sel.x 1 0 p1dir.x p1in.x inch=4 a4? pad logic sd16ae.x p1irq.x d en module x in 1 0 module x out p1out.x note: x = 2 p1.2/ta1/a4? 1 0 av ss interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x port p1 (p1.2) pin functions pin name (p1 x) x function control bits / signals pin name (p1.x) x function p1dir.x p1sel.x sd16ae.x p1.2/ta1/a4? 2 p1.2? input/output 0/1 0 0 timer_a3.cci1a 0 1 0 timer_a3.ta1 1 1 0 a4? (see notes 3, 4) x x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the sd16ae.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 4. negative input to sd16_a (a4?) connected to v ss if corresponding sd16ae.x bit is cleared.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 43 post office box 655303 ? dallas, texas 75265 port p1 pin schematic: p1.3, p1.5, p1.7, input/output with schmitt trigger and analog functions bus keeper en direction 0: input 1: output p1sel.x 1 0 p1dir.x p1in.x inch=y ay+ pad logic sd16ae.x p1irq.x d en module x in 1 0 module x out p1out.x note: x = 3,5,7 y = 4,3,2 p1.3/ta2/a4+ p1.5/taclk/aclk/a3+ p1.7/a2+ interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 44 post office box 655303 ? dallas, texas 75265 port p1 (p1.3, p1.5, p1.7) pin functions pin name (p1 x) x function control bits / signals pin name (p1.x) x function p1dir.x p1sel.x sd16ae.x p1.3/ta2/a4+ 3 p1.3? input/output 0/1 0 0 timer_a3.cci2a 0 1 0 timer_a3.ta2 1 1 0 a4+ (see note 3) x x 1 p1.5/taclk/aclk/a3+ 5 p1.5? input/output 0/1 0 0 timer_a3.taclk/inclk 0 1 0 aclk 1 1 0 a3+ (see note 3) x x 1 p1.7/a2+ 7 p1.5? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 a2+ (see note 3) x x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the sd16ae.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 45 post office box 655303 ? dallas, texas 75265 port p1 pin schematic: p1.4, input/output with schmitt trigger and analog functions bus keeper en direction 0: input 1: output p1sel.x 1 0 p1dir.x p1in.x inch=3 a3? pad logic sd16ae.x interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x p1irq.x 1 0 p1out.x note: x = 4 p1.4/a3?/oa1i0/dac0 1 0 av ss dac12ops dac12ops dac0 oa1 ? + dv ss port p1 (p1.4) pin functions pin name (p1 x) x function control bits / signals pin name (p1.x) x function p1dir.x p1sel.x sd16ae.x oapx (oa1) dac12ops p1.4/a3?/oa1i0/dac0 4 p1.4? input/output 0/1 0 0 xx 0 n/a 0 1 0 xx 0 dvss 1 1 0 xx 0 a3? (see notes 3, 4) x x 1 xx 0 oa1i0 x x 1 00 0 dac0 (see note 5) x x x xx 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the sd16ae.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 4. negative input to sd16_a (a3?) connected to av ss if corresponding sd16ae.x bit is cleared. 5. setting the dac12ops bit also disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 46 post office box 655303 ? dallas, texas 75265 port p1 pin schematic: p1.6, input/output with schmitt trigger and analog functions bus keeper en direction 0: input 1: output p1sel.x 1 0 p1dir.x p1in.x inch=2 a2? pad logic sd16ae.x interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x p1irq.x 1 0 p1out.x note: x = 6 p1.6/a2?/oa0i0 1 0 av ss ? + oa0/1 dv ss port p1 (p1.6) pin functions pin name (p1 x) x function control bits / signals pin name (p1.x) x function p1dir.x p1sel.x sd16ae.x oapx (oa0) oapx (oa1) p1.6/a2?/oa0i0 6 p1.6? input/output 0/1 0 0 xx xx n/a 0 1 0 xx xx dvss 1 1 0 xx xx a2? (see notes 3, 4) x x 1 xx xx oa0i0 (see note 5) x x 1 00 or 01 xx oa0i0 (see note 5) x x 1 xx 01 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the sd16ae.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 4. negative input to sd16_a (a2?) connected to av ss if corresponding sd16ae.x bit is cleared. 5. oa0i0 connected to pin if for oa0 the oapx bits are cleared or set to 01, or if for oa1 the oapx bits are set to 01.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 47 post office box 655303 ? dallas, texas 75265 port p2 pin schematic: p2.0 to p2.1, input/output with schmitt trigger, lcd and analog functions bus keeper en direction 0: input 1: output p2sel.x 1 0 p2dir.x p2in.x lcds12 segment sy pad logic p2irq.x 1 0 p2out.x note: x = 0,1 y = 13,12 p2.0/s13/sw0c p2.1/s12/sw1c interrupt edge select q en set p2sel.x p2ies.x p2ifg.x p2ie.x swctl.swclt2 (sw0c) swctl.swclt6 (sw1c) av ss dv ss port p2 (p2.0, p2.1) pin functions pin name (p2 x) x function control bits / signals pin name (p2.x) x function p2dir.x p2sel.x lcds12 p2.0/s13/sw0c 0 p2.0? input/output 0/1 0 0 sw0c (see notes 3, 4) x 1 0 s13 x x 1 p2.1/s12/sw1c 1 p2.1? input/output 0/1 0 0 sw1c (see notes 3, 4) x 1 0 s12 x x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the p2sel.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents w hen applying analog signals. 4. the low impedance switch to ground is closed by setting the corresponding bits in swctl register.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 48 post office box 655303 ? dallas, texas 75265 port p2 pin schematic: p2.2 to p2.7, input/output with schmitt trigger, lcd and analog functions bus keeper en direction 0: input 1: output p2sel.x 1 0 p2dir.x p2in.x lcds4/8/12 segment sy pad logic dv ss p2irq.x 1 0 p2out.x note: x = 2 to 7 y = 11 to 6 p2.2/s11 p2.3/s10 p2.4/s9 p2.5/s8 p2.6/s7 p2.7/s6 interrupt edge select q en set p2sel.x p2ies.x p2ifg.x p2ie.x dv ss
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 49 post office box 655303 ? dallas, texas 75265 port p2 (p2.0 to p2.7) pin functions pin name (p2 x) x function control bits / signals pin name (p2.x) x function p2dir.x p2sel.x lcds12 p2.2/s11 2 p2.2? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s11 x x 1 p2.3/s10 3 p2.3? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s10 x x 1 p2.4/s9 4 p2.4? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s9 x x 1 p2.5/s8 5 p2.5? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s8 x x 1 p2.6/s7 6 p2.6? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s7 x x 1 p2.7/s6 7 p2.7? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s6 x x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 50 post office box 655303 ? dallas, texas 75265 port p5 pin schematic: p5.0, p5.1, p5.5 to p5.7, input/output with schmitt trigger and lcd functions bus keeper en direction 0: input 1: output p5sel.x 1 0 p5dir.x p5in.x lcds0/4 segment sy pad logic dv ss 1 0 p5out.x note: x = 0,1,5,6,7 y = 1,0,2,3,4 p5.0/s1 p5.1/s0 p5.5/s2 p5.6/s3 p5.7/s4 dv ss
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 51 post office box 655303 ? dallas, texas 75265 port p5 (p5.0, p5.1, p5.5, p5.6) pin functions pin name (p5 x) x function control bits / signals pin name (p5.x) x function p5dir.x p5sel.x lcds0 p5.0/s1 0 p5.0? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s1 x x 1 p5.1/s0 1 p5.1? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s0 x x 1 p5.5/s2 5 p5.5? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s2 x x 1 p5.6/s3 6 p5.6? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s3 x x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. port p5 (p5.7) pin functions pin name (p5 x) x function control bits / signals pin name (p5.x) x function p5dir.x p5sel.x lcds4 p5.7/s4 7 p5.7? input/output 0/1 0 0 n/a 0 1 0 dvss 1 1 0 s4 x x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 52 post office box 655303 ? dallas, texas 75265 port p5 pin schematic: p5.2 to p5.4, input/output with schmitt trigger and lcd functions bus keeper en direction 0: input 1: output p5sel.x 1 0 p5dir.x p5in.x lcd signal pad logic dv ss 1 0 p5out.x note: x = 2 to 4 p5.2/com1 p5.3/com2 p5.4/com3 dv ss port p5 (p5.2 to p5.4) pin functions pin name (p5 x) x function control bits / signals pin name (p5.x) x function p5dir.x p5sel.x p5.2/com1 2 p5.2? input/output 0/1 0 com1 x 1 p5.3/com2 3 p5.3? input/output 0/1 0 com2 x 1 p5.4/com3 4 p5.4? input/output 0/1 0 com3 x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 53 post office box 655303 ? dallas, texas 75265 port p6 pin schematic: p6.0, p6.2, input/output with schmitt trigger and analog functions bus keeper en direction 0: input 1: output p6sel.x 1 0 p6dir.x p6in.x inch=0/1 # ay+ # pad logic 1 0 dv ss p6out.x note: x = 0,2 y = 0,1 # signal from or to sd16 p6.0/a0+/oa0o p6.2/a1+/oa1o ? + oa0/1 port p6 (p6.0, p6.2) pin functions pin name (p6 x) x function control bits / signals pin name (p6.x) x function p6dir.x p6sel.x p6.0/a0+/oa0o 0 p6.0? input/output 0/1 0 a0+/oa0o (see note 3) x 1 p6.2/a1+/oa1o 2 p6.2? input/output 0/1 0 a1+/oa1o (see note 3) x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the p6sel.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents w hen applying analog signals.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 54 post office box 655303 ? dallas, texas 75265 port p6 pin schematic: p6.1, p6.3, input/output with schmitt trigger and analog functions bus keeper en direction 0: input 1: output p6sel.x 1 0 p6dir.x p6in.x inch=0/1 # ay? # pad logic 1 0 dv ss p6out.x note: x = 1,3 y = 0,1 # signal from or to sd16 p6.1/a0?/oa0fb p6.3/a1?/oa1fb ? + oa0/1 port p6 (p6.1, p6.3) pin functions pin name (p6 x) x function control bits / signals pin name (p6.x) x function p6dir.x p6sel.x p6.1/a0?/oa0fb 1 p6.1? input/output 0/1 0 a0?/oa0fb (see note 3) x 1 p6.3/a1?/oa1fb 3 p6.3? input/output 0/1 0 a1?/oa1fb (see note 3) x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the p6sel.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents w hen applying analog signals.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 55 post office box 655303 ? dallas, texas 75265 port p6 pin schematic: p6.4 to p6.7, input/output with schmitt trigger and analog functions bus keeper en direction 0: input 1: output p6sel.x 1 0 p6dir.x p6in.x 1 0 dv ss p6out.x note: x = 4 to 7 p6.4/oa0i1 p6.5/oa0i2 p6.6/oa1i1 p6.7/oa1i2 ? + oa0/1 pad logic port p6 (p6.4 to p6.7) pin functions pin name (p6 x) x function control bits / signals pin name (p6.x) x function p6dir.x p6sel.x p6.4/oa0i1 4 p6.4? input/output 0/1 0 oa0i1 (see note 3) x 1 p6.5/oa0i2 5 p6.5? input/output 0/1 0 oa0i2 (see note 3) x 1 p6.6/oa1i1 6 p6.6? input/output 0/1 0 oa1i1 (see note 3) x 1 p6.7/oa1i2 7 p6.7? input/output 0/1 0 oa1i2 (see note 3) x 1 ? default after reset (puc/por) notes: 1. n/a: not available or not applicable. 2. x: don?t care. 3. setting the p6sel.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents w hen applying analog signals.
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 56 post office box 655303 ? dallas, texas 75265 jtag pins tms, tck, tdi/tclk, tdo/tdi, input/output with schmitt trigger or output tdi tdo tms tdi/tclk tdo/tdi controlled by jtag tck tms tck dv cc controlled by jtag test jtag and emulation module dv cc dv cc burn and test fuse rst/nmi g d s u g d s u tck tau ~ 50 ns brownout controlled by jtag
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 57 post office box 655303 ? dallas, texas 75265 jtag fuse check mode msp430 devices that have the fuse on the tdi/tclk terminal have a fuse check mode that tests the continuity of the fuse the first time the jtag port is accessed after a power-on reset (por). when activated, a fuse check current (i (tf) ) of 1 ma at 3 v can flow from the tdi/tclk pin to ground if the fuse is not burned. care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. activation of the fuse check mode occurs with the first negative edge on the tms pin after power up or if the tms is being held low during power up. the second positive edge on the tms pin deactivates the fuse check mode. after deactivation, the fuse check mode remains inactive until another por occurs. after each por the fuse check mode has the potential to be activated. the fuse check current only flows when the fuse check mode is active and the tms pin is in a low state (see figure 21). therefore, the additional current flow can be prevented by holding the tms pin high (default condition). the jtag pins are terminated internally and therefore do not require external termination. time tms goes low after por tms i (tf) i tdi/tclk figure 21. fuse check mode current
msp430fg42x0 mixed signal microcontroller slas556a ? july 2007 ? revised august 2007 58 post office box 655303 ? dallas, texas 75265 data sheet revision history literature number summary slas556 product preview data sheet release slas556a production data data sheet release note: page and figure numbers refer to the respective document revision.
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples msp430fg4250idl active ssop dl 48 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430fg4250 msp430fg4250idlr active ssop dl 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430fg4250 msp430fg4250irgzr active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 fg4250 msp430fg4250irgzt active vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 fg4250 msp430fg4260idl active ssop dl 48 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430fg4260 msp430fg4260idlr active ssop dl 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430fg4260 msp430fg4260irgzr active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 fg4260 msp430fg4260irgzt active vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 fg4260 MSP430FG4270IDL active ssop dl 48 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430fg4270 MSP430FG4270IDLr active ssop dl 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430fg4270 msp430fg4270irgzr active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 fg4270 msp430fg4270irgzt active vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 fg4270 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined.
package option addendum www.ti.com 11-apr-2013 addendum-page 2 pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430fg4250idlr ssop dl 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 q1 msp430fg4260idlr ssop dl 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 q1 MSP430FG4270IDLr ssop dl 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) msp430fg4250idlr ssop dl 48 1000 367.0 367.0 55.0 msp430fg4260idlr ssop dl 48 1000 367.0 367.0 55.0 MSP430FG4270IDLr ssop dl 48 1000 367.0 367.0 55.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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